Akademik Məlumat İdarəetmə Sistemi
Silicon, vol.14, no.13, pp.8031-8043, 2022 (SCI-Expanded, Scopus)
Due to unrelenting progression of silicon technology, the power dissipation has become important concern in nanometer regime. To limit the power consumption and to improve the performance of digital system different architecture level low power techniques are available. This article presents the performance investigation of the proposed different CNTFET SRAM cells with the incorporation of low power techniques by using Cadence Virtuoso at 32 nm technology. In this workdifferent low power techniques like Sleep, variation of Sleep (using header/footer switch), Zigzag, Stack, Sleep stack, Leakage Feedback (LF), Sleepy Keeper (SK), Leakage Feedback with Stack (LFS) and Sleep Stack with Keeper (SSK) approaches are incorporated in CNTFET SRAM cell.By incorporating different low power techniques in CNTFET SRAM cell, noteworthy reduction in design metrics of SRAM cell is being observedfor example with sleepy keeper (leakage feedback with stack) approach 84.26% (81.13%) reduction in average power dissipation, 38.12% (43.01%) reduction in delay and 9.15% (20.80%) reduction in leakage power dissipation is observed. Stability of memory cellthat ismajor design constraint of SRAM cell, is also examined for the proposed CNTFET SRAM cells by using butterfly curve and analytic N-curve procedure. Although cell area gets increased at certain level, but performance indices of the SRAM cell will get improved significantly, hence system performance can be increased.